The present invention generally relates to photolithography, and more specifically relates to methods for optimizing the illumination of masks in a photolithography process, in order to achieve maximum common process window.
Making a semiconductor device, such as an integrated circuit (IC), involves using photolithography to form patterns on a wafer, where the patterns correspond to complex circuitry. During the process, the patterns are initially formed on a reticle or mask, and then the patterns are exposed on the wafer by shining a light through, or illuminating, the mask.
Depth of focus (DOF) indicates the range of distances around a focal plane where the image quality is sharp. It is important to optimize the illumination of a mask to achieve maximum common DOF, as this results in the best exposure of the wafer.
Mask error factor limits the amount of a common process window which is useable. Additionally, Optical Proximity Correction (OPC) is common in the industry and involves the pre-compensation of predicted defects of a circuit design. The focus-exposure window of features which have not been adjusted based on OPC techniques is not representative of the common process window of the design after OPC techniques have been applied. FIG. 1 provides a flow chart which illustrates a prior art illumination optimization technique. Current methods of optimizing the illumination of masks are based on the focus-exposure window, and do not take into account mask error constraints or OPC. As a result, current illumination optimization techniques are sub-optimal. For example, they do not make readily apparent the difference between common process window of different mask types, such as attenuated phase shift masks (PSM) and binary masks.